- Basic electronics
- Digital representation

- What is an analog-digital converter?
- How does the ADC convert a signal?
- Flash ADCs
- Pipelined ADCs
- Successive Approximation Register (SAR) converters
- Intregating or Dual-slope converters
- Sigma-Delta converters
- Characteristics of ADCs
- ADC coding scheme
- Offset
- Gain error
- Integral and Differential Nonlinearity
- Resolution
- Conversion speed
- When designing an ADC

An Analog-Digital Converter (ADC) is a widely used electronic component that converts an analog electric signal (usually a voltage) into a digital representation. The ADCs are at the front-end of any digital circuit that needs to process signals coming from the exterior world. Its schematic symbol is:

The output of a microphone, the voltage at a photodiode or the signal of an accelerometer are examples of analog values that need to be converted so that a microprocessor can work with them.

Many ways have been developed to convert an analog signal, each with its strengths and weaknesses. The choice of the ADC for a given application is usually defined by the requirements you have: if you need speed, use a fast ADC; if you need precision, use an accurate ADC; if you are constrained in space, use a compact ADC.

All ADCs work under the same principle: they need to convert a signal to a certain number of bits

Let's talk about the following ADCs (although there are more):

- Flash
- Pipelined
- Successive-Approximations Register (SAR)
- Integrating or Dual-slope
- Sigma Delta (
ΣΔ )

Flash converters have a resistive ladder that divides the reference voltage in

The Priority Encoder has to find the position of the last comparator
with high output, starting from the bottom. That means that it should
find the position where neighboring comparators have different outputs
(all below have output high and all above have output low). That can be
simply done by XORing the outputs of neighboring comparators and feeding
their outputs to a digital encoder. Only one XOR has its output active
and the encoder will translate that position into a binary
representation. If there are 2^{N} comparators, the encoder outputs a N-bit number.

- Very fast, converts instantly

- It doubles in size for each bit added to the representation.
N bits require2N−1 comparators. - It has a high input capacitance (the input capacitance of a comparator multiplied by
2N−1 ) - It consumes a lot of power

Pipelined converters convert the input in a number of steps proportional to the number of bits. At each step, the input signal is compared to half the reference value. If it is higher, half the reference value is subtracted to the input and the bit corresponding to that step is 1. Otherwise, it is 0. In either cases, the remaining value is doubled and passed to the next stage. Note that each stage is taking care of one bit, so a new value can be applied to the input every cycle.

- The number of stages increases only with the number of bits
- As fast as the flash ADC

- High latency - For any analog value, it takes
N cycles to output the corresponding binary representation - Any error introduced in the doubling or subtraction operations passes to the following stages

A Successive Approximation Register converter evaluates each bit at a
time, from the most to the least significant bits. They successively
approach the output of a digital-analog converter (DAC) in them to the
input voltage. The input of the DAC is stored in a

Let's see the flow of this ADC with the aid of the picture below. First,
the analog signal is sampled and kept fixed. If the input value is
changed during the conversion, the result can be completely wrong. Then,
the bit **the converter is generating a signal from the register that is successively approximating the input value** (hence its name).

SAR ADC architecture

In a nutshell, a SAR follows these two steps for each bit, from most to least significant bit, after resetting the register value to 0:

**Comparison:**Set bit to 1 and compare the output of the DAC with the input voltage**Latching:**Latch the result of the comparator to the same bit in the register

0

1

2

3

4

5

6

7

cycles

0.0

0.2

0.4

0.6

0.8

The slider below controls the input voltage of an 8-bit (8 cycles) SAR ADC. When you change the input voltage, you can see in the plot above that the output of the DAC tends to get closer to the input signal as more bits are defined. To see if a particular bit was set or cleared during the latching phase, you have to see if the output of the DAC at the next cycle is above or below the value of the previous cycle.

- It uses only one comparator
- Low power consumption

- The DAC grows with the number of bits
- They take as many cycles to convert the signal as the number of bits
- The component mismatch in the DAC limits its linearity (and therefore of the ADC) to around 12bits

The dual-slope are very precise, but slow converters that use counters to generate the output. As its name suggests, this converter has 2 phases, the first where a voltage ramps up with a certain slope, and the second where the same voltage ramps down with a different slope.

First, **a voltage ramps up with slope proportional to the input voltage Vin for a fixed period of time**.
This can be achieved, for example, with a current source proportional
to the input voltage charging a capacitor. The voltage at the end of
that integration time is:

Second, **the output voltage ramps down with slope proportional to a fixed voltage Vref**.
Note that in the first phase, the slope is variable and the integration
time is fixed. Now, the slope is fixed and the integration time is
variable:

0.00

0.25

0.50

0.75

1.00

1.25

1.50

1.75

time/tint

0.0

0.2

0.4

0.6

0.8

The slider below controls the input voltage of the
ADC. When you change the input voltage, you can see in the plot above
that a) the slope of the ramp up changes with

- Very precise. The sources of errors are only the comparison with zero and the clock period.

- Slow. The ADC needs time to ramp up and down the output voltage and doubles with each bit added to the representation, for a fixed clock period.

The sigma-delta converter is unique in that **it samples the signal in a much higher frequency than the Nyquist frequency**. For that reason it is also called **oversampling converter**. It converts the input signal **To convert that bit stream into a binary code, a decimation filter is used**.

Sigma-Delta ADC architecture

0

5

10

15

20

25

30

35

40

45

cycles

-1.0

-0.5

0.0

0.5

The slider below controls the input voltage of a Sigma-Delta ADC. You can see that the number of cycles that

Oversampling is the sampling at a frequency much higher than the Nyquist frequency, i.e., at a much higher frequency than the double of the maximum frequency of the signal. Although I talk about oversampling in the sigma-delta converters, oversampling can be applied in any converter. Oversampling is often associated to sigma-delta converters because they can only operate in this mode, while others can operate closer to the Nyquist frequency.

So what is so good about oversampling? The Quantization noise has a power related to the range of the LSB (Q):

0

100

200

300

400

500

600

700

800

frequency

0.0

0.2

0.4

0.6

0.8

W/Hz

Signal PSD | |

Quantization noise PSD |

The slider below controls the sampling frequency of
the sigma-delta converter. As the sampling frequency increases, and
since the power remains the same, the power per Hertz is reduced.

Afterwards, an analog or digital low-pass filter can be applied to filter out the frequencies above the band of interest (the band where the signal lies).

But how does oversampling influences the Signal-Noise Ratio? Let's say that we double the sampling frequency (the rectange doubles its width, but reduces its height by half). Keeping the low-pass filter corner frequency constant, the quantization noise is reduced by half, which doubles the SNR. So, to the SNR in decibels:

Added to the oversampling frequency, and a particular benefit of the sigma-delta converters, **the noise spectrum is shaped by a high-pass filter caused by the integrator inside the ADC**. Imagine the simplified version of the ADC shown below:

Linearized version of the Sigma-Delta ADC

We removed the 1-bit ADC, 1-bit DAC and the latch to make the system linear.

The decimation filter converts the bitstream at the output of the
converter into a binary representation. If the bitstream is made of K
bits, the decimation filter counts the number of 1s and stores the
number in log_{2}(K) bits.

- Due to a large oversampling, the quantization noise spectral density is reduced
- It allows noise shaping (quantization noise is attenuated at lower frequencies)
- Very simple circuits

- Requires the decimation filter in the end
- Only useful in applications requiring low sampling rate, such as audio

Since the ADC converts a continuous signal to a discrete representation,
the ADC coding scheme can be represented by a staircase, in which a
range of values of the input correspond to the same step. That range

The offset is a deviation of the staircase in the input axis. The output code is changing at the wrong input, but the offset is equal for the whole range.

An offset of the converter can be caused by an offset in the comparator of a SAR converter.

The gain error is a change in the slope of the staircase. It accumulates the error, leading to larger errors for higher output codes.

A gain error can be caused by an uncalibrated voltage reference. The output code will scale with the voltage reference and different voltage references will lead to different switching points of the output code.

Integral Nonlinearity (INL) and Differential Nonlinearity (DNL) are two different ways of measuring the nonlinearity of a converter. In the ideal staircase, it is necessary to change the input by 1 LSB to change the output code by 1 LSB.

The DNL measures, for each code, how much more or less the input has to change to reach the next code in relation to the previous step.

The INL indicates how much the real transfer function deviates from the
ideal staircase. Therefore, it measures, for each code, how much more or
less the input has to change to reach the next code in relation to the
ideal staircase. If

If the change is 1 LSB, the INL = 0; if the change is more than 1 LSB, the INL if positive; if the change is less than 1 LSB, the INL is negative.

Resolution is defined by the number of bits the output code has. This
metric means little without accounting with the errors described above.
For instance, an ADC with 12bit and DNL = 0 is better than an ADC with
15 bit and DNL

The conversion speed, defined as samples per second, measures how fast the ADC can accurately convert analog values.

You may have noticed that all analog-digital converters have comparators. When designing any ADC, the specifications of the comparators are of paramount importance. That is because:

- They must have an input-referred offset voltage below 1 LSB
- They must have an input-referred noise below 1 LSB
- They must resolve a comparison for differential inputs below 1 LSB